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讲座通知-东京工业大学Akira Matsuzawa教授来学院做学术报告

发布日期:2016-10-18  浏览次数:

 

讲座主题:Advanced mixed signal IC design

讲座时间:20161021 上午9:20-10:30

讲座地点: 中二楼-208

主讲嘉宾:Dr. Akira MATSUZAWA(东京工业大学)

主讲人简介:

说明: Matsu_trimAkira Matsuzawa received B.S., M.S., and Ph. D. degrees in electronics engineering from Tohoku University, Sendai, Japan, in 1976, 1978, and 1997 respectively.  In 1978, he joined Matsushita Electric Industrial Co., Ltd (Panasonic). Since then, he has been working on research and development of analog and Mixed Signal LSI technologies; ultra-high speed ADCs, intelligent CMOS sensors, RF CMOS circuits, and digital read-channel technologies for DVD systems. From 1997 to 2003, he was a general manager in advanced LSI technology development center. On April 2003, he joined Tokyo Institute of Technology and he is professor on physical electronics. Currently he is researching in mixed signal technologies; RF CMOS circuit design for SDR and high speed data converters. He served the guest editor in chief for special issue on analog LSI technology of IEICE transactions on electronics in 1992, 1997, and 2003, the Vice-Program Chairman for International Conference on Solid State Devices and Materials (SSDM) in 1999 and 2000, the guest editor for special issues of IEEE Transactions on Electron Devices, the committee member for analog technology in ISSCC, the educational session chair of A-SSCC, the executive committee member of VLSI symposia, the IEEE SSCS elected Adcom, the IEEE SSCS Distinguished lecturer, the chapter chair of IEEE SSCS Japan Chapter, and the vice president of Japan Institution of Electronics Packaging. He received the IR100 award in 1983, the R&D100 award and the remarkable invention award in 1994, and the ISSCC evening panel award in 2003, 2005, 2015. He is an IEEE Fellow since 2002, and an IEICE Fellow since 2010.

讲座内容:

1. Ultra-high data rate millimeter wave CMOS transceivers

60-100GHz CMOS transceivers attained world’s highest data rate of 48-56 Gbps.

 Low phase noise injection locking 60GHz QVCO and wide band impedance matching using resistive feedback. Future prospect of ultra-high data rate wireless communication.

2. Ultra-low power CMOS analog to digital converters

 Dynamic analog circuits, 12b SAR ADC, and fully passive delta-sigma ADC.

3. High performance PLLs

 Low jitter PLL with injection locking method, fully synthesizable PLL, ADC PLL, High precision Time to Digital converter, and Full digital PLL using charge-pump and SAR ADC.

4. Fully automated mixed signal circuit design

 Fully automated design method for mixed signal circuits such as DACs and ADCs

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